1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices, and more particularly to a non-volatile semiconductor memory device that performs data writing for a prescribed unit area at a time.
2. Description of the Background Art
In recent years, a flash memory has come into use as a file storage medium, and storage capacity thereof has been increased. As a way of increasing the storage capacity, a technique for writing data of at least two bits in one cell has been widely discussed.
FIG. 10 is a schematic diagram showing a structure of a memory cell MC in a flash memory.
Referring to FIG. 10, the memory cell MC of the flash memory includes a source 22 and a drain 23 that are n+ regions formed on a p type substrate 21. Memory cell MC further includes a floating gate 24 and a control gate 25. Floating gate 24 and control gate 25 are stacked one on the other on p type substrate 21, insulated from each other by an insulating film 26. In particular, the insulating film between floating gate 24 and control gate 25 is also called an inter-poly insulating film 26a, and the insulating film between floating gate 24 and p type substrate 21 is also called a tunnel insulating film 26b. Accordingly, memory cell MC corresponds to an n channel field effect transistor formed on p type substrate 21.
Control gate 25 is coupled to a word line WL for selecting the memory cell MC. Source 22 and drain 23 are coupled to a source line SL and a bit line BL, respectively.
In memory cell MC of a data erased state as an initial state, an electron 27 is drawn out of floating gate 24.
Specifically, assume that a negative high voltage Vnn and a ground voltage GSS are applied to control gate 25 and source 22, respectively, of memory cell MC. In this case, in the memory cell MC, electron 27 is drawn from floating gate 24 by Fowler-Nordheim tunneling, so that data is erased.
Data writing to memory cell MC is carried out by injection of electron 27 into floating gate 24 by the Fowler-Nordheim tunneling.
Specifically, under a condition where source line SL is open, a high voltage Vpp and ground voltage GSS are applied to control gate 25 and drain 23 via word line WL and bit line BL, respectively. This causes the Fowler-Nordheim tunneling, so that electron 27 is injected to floating gate 24, and thus, data is written therein. If high voltage Vpp and a write inhibit voltage Vdi are applied to control gate 25 and drain 23, respectively, then the data writing is not effected.
Here, the threshold voltage Vth of memory cell MC in the data written state with electron 27 having been injected to floating gate 24 becomes higher than that in the data erased state.
Therefore, when data is written into memory cell MC in the data erased state, the stored data can be read out according to the level of threshold voltage Vth of the memory cell MC. For the data reading, bit line BL is precharged in advance, which is discharged for a prescribed period of time by applying a constant voltage to word line WL coupled to control gate 25, and then, the resulting potential of bit line BL is detected.
Specifically, at the time of data reading, bit line BL is precharged in advance to a prescribed voltage Vdr. Source line SL is provided with ground voltage GSS. A prescribed voltage Vwr for data reading is applied to selected word line WL for a prescribed period of time. Control gate 25 of corresponding memory cell MC is thus set to prescribed voltage Vwr.
When these voltages Vwr and Vdr are properly set taking into account the threshold voltage Vth of memory cell MC with data written therein, memory cell MC would not turn on if data writing has been completed therefor, so that it maintains the precharged charges. On the contrary, memory cell MC would turn on if the data writing has not been completed yet, in which case the precharged charges are discharged via memory cell MC to source line SL, so that the potential of bit line BL is decreased. Detection of the amount of charges remained on bit line BL thereafter enables the data reading.
Thus, according to the degree of injection of electrons 27 to floating gate 24, data can be written into each memory cell MC in a non-volatile manner, and the stored data can be read out.
FIG. 11 shows distribution of threshold voltages Vth of memory cells in a flash memory.
Referring to FIG. 11, a memory cell in the data written state (in distribution 2) with its stored data level being xe2x80x9c0xe2x80x9d has threshold voltage Vth higher than that of a memory cell in the data erased state (in distribution 1) with its stored data level being xe2x80x9c1xe2x80x9d.
In respective memory cell groups in the data written state and in the data erased state, their threshold voltages Vth exhibit variation (e.g., from Va to Vb in distribution 2). Therefore, to read out data from these memory cells, the data reading level should be set at a level enabling discrimination of the respective threshold voltages Vth in consideration of the variation therein. For example, the data reading level can be set to threshold voltage Va. In this case, the data level of a memory cell with its threshold voltage exceeding Va can be set to xe2x80x9c0xe2x80x9d, and the data level of a memory cell with its threshold voltage not greater than Va can be set to xe2x80x9c1xe2x80x9d.
In the case of multi-valued data of greater than 2 bits, distribution of threshold voltages Vth of the memory cells storing data in various levels should be tighter in consideration of variation thereof. That is, the variation of the threshold voltages in the respective levels of the data writing should be restricted more strictly.
A data writing sequence of a conventional flash memory will now be described with reference to FIG. 12.
Referring again to FIG. 11, assume that a plurality of memory cells in the data erased state (in distribution 1) are made to attain the data written state with their threshold voltages Vth falling within a range between Va (V) and Vb (V).
In a flash memory, a condition of data writing operation is set for each unit writing region that becomes a target of data writing operation at one time (or xe2x80x9cunit writing operationxe2x80x9d). Hereinafter, the prescribed unit region as the target of the unit writing operation is also referred to as a xe2x80x9csectorxe2x80x9d. One sector corresponds to a memory cell group selected by one word line.
When a data writing command is input, the data writing sequence starts at step S1. Here, the number of times of unit writing operations N is set to 1 (START).
Next, the data writing operation is carried out for each sector (step S1). The data writing condition will now be described.
In general, at the time of unit writing operation in the flash memory, a data writing pulse, or a voltage signal having prescribed voltage amplitude and pulse width, is applied to the control gate of a memory cell. In other words, the condition of the unit writing operation is set by the voltage amplitude VWW and the pulse width or application time tP of the data writing pulse.
FIG. 13 is a table for use in setting the condition of unit writing operation of the conventional data writing sequence. For example, when the number of times of unit writing operations having been conducted (hereinafter, also referred to as xe2x80x9cunit writing operation totalxe2x80x9d) N is less than a prescribed number Y, the application time tP as the unit writing operation condition is set to T1. When unit writing operation total N is equal to prescribed number Y, application time tP is set to T2. When total N is greater than prescribed number Y, application time tP is set to T2xc3x97P(Nxe2x88x92Y) (T2: initial term, P: power coefficient). Thus, application time tP increases exponentially after unit writing operation total N has exceeded prescribed number Y.
Next, to determine whether the data writing is properly conducted, a prescribed threshold voltage Vth=Va is applied to read data (step S2).
If all the memory cells have attained threshold voltages greater than prescribed level of Va, it is determined that the data writing has been succeeded, so that the data writing sequence is terminated. Otherwise, it is determined NG (no good), and the operation goes to step S4 after setting unit writing operation total N to N+1 (step S3).
In step S4, it is determined whether unit writing operation total N is within a prescribed number K. If the total N has exceeded prescribed number K, it is determined NG and the data writing sequence is terminated. If total N is within prescribed number K, the operation proceeds to step S5.
If the data writing is conducted to the memory cell for which the data writing has already been completed, electrons would be injected excessively, resulting in an over-programmed memory cell. Thus, before resuming the initial step S1, the memory cell for which data writing has been completed is eliminated from the target of the data writing (step S5). The unit writing operation is then conducted again for the memory cells for which the data writing has not yet been completed.
With such a conventional data writing method, however, the speed of data writing would vary for each lot at the end of the wafer process, or it would change through repetition of data erasing and writing. Thus, using the same data writing sequence for every lot would result in failure in the data writing sequence, as threshold voltages Vth of memory cells in some lots might be out of a specific range, e.g., greater than Vb in FIG. 11. In addition, if the data writing is slow in speed, determination of failure would take a long period of time, since the error in data writing would not be found until the sequence is completed.
The present invention is made to solve the above-described problems, and its object is to provide a non-volatile semiconductor memory device that prevents failure of a data writing sequence and allows judgement of a data writing error in an early stage.
The non-volatile semiconductor memory device of the present invention includes: a memory cell array region having a plurality of memory cells arranged in rows and columns for storing data in a non-volatile manner, a plurality of word lines provided corresponding to the rows of the memory cells, and a plurality of bit lines provided corresponding to the columns of the memory cells; and a control unit controlling data writing for selected ones of the plurality of memory cells corresponding to a selected one of the plurality of word lines as a target of the data writing. The control unit performs: designation of a unit writing operation that is carried out repeatedly for the selected memory cells until the data writing is completed; a first judging operation carried out every time the unit writing operation is finished, for confirmation of as to whether the data writing has been completed for at least one of the selected memory cells; and a second judging operation carried out every time the unit writing operation is finished after the first judging operation has confirmed the completion of the data writing, for confirmation of as to whether the data writing has been completed for all the selected memory cells.
Preferably, the control unit counts the number of times of the designation of the unit writing operation, and terminates the designation of the data writing for the selected memory cells when the number of times of the designation of the unit writing operation repeated until the first judging operation confirms the completion of the data writing has reached a prescribed number.
According to the non-volatile semiconductor memory device above, it is possible to detect failure in data writing in an early stage by performing the first and second judging operations.
Preferably, the non-volatile semiconductor memory device further includes a storage unit for storing a first setting condition of the unit writing operation repeated until the data writing is completed for at least one of the selected memory cells, and a second setting condition of the unit writing operation repeated until the data writing is completed for all the selected memory cells. The first setting condition and the second setting condition are different from each other.
According to the non-volatile semiconductor memory device above, the data writing can be performed rapidly by differentiating the first setting condition of the unit writing operation conducted until the first judging operation is completed and the second setting condition of the unit writing operation conducted until the second judging operation is completed.
Specifically, the control unit counts the number of times of the designation of the unit writing operation, and designates the unit writing operation based on either one of the first and second setting conditions stored in the storage unit. In the storage unit, the first and second setting conditions each include a voltage amplitude of a pulse voltage signal being applied to the selected word line in the unit writing operation, and a voltage application time of the pulse voltage signal. The first setting condition has the constant voltage amplitude and the constant voltage application time. The second setting condition has the constant voltage amplitude and the voltage application time varied according to the number of times of the designation of the unit writing operation.
Alternatively, the control unit counts the number of times of the designation of the unit writing operation, and designates the unit writing operation based on either one of the first and second setting conditions stored in the storage unit. In the storage unit, the first and second setting conditions each include a voltage amplitude of a pulse voltage signal being applied to the selected word line in the unit writing operation, and a voltage application time of the pulse voltage signal. The first setting condition has the constant voltage amplitude and the voltage application time varied according to the number of times of the designation of the unit writing operation. The second setting condition has the constant voltage amplitude and the voltage application time varied according to the number of times of the designation of the unit writing operation.
According to the non-volatile semiconductor memory device above, the voltage application time in each of the first and second setting conditions can be made variable, so that high-precision data writing is enabled.
Alternatively, the non-volatile semiconductor memory device further includes a storage unit for storing a setting condition of the unit writing operation conducted repeatedly, after the first judging operation has confirmed the completion of the data writing, until the data writing for all the selected memory cells is completed. The control unit further counts the number of times of the designation of the unit writing operation, and designates the unit writing operation based on the setting condition, according to the number of times of the designation of the unit writing operation that was necessary for completion of the data writing. of at least one of the selected memory cells.
Specifically, the setting condition stored in the stored unit has a voltage application time of a pulse voltage signal that is applied to the selected word line in the unit writing operation, and a voltage amplitude of the pulse voltage signal varied according to the number of times of the designation of the unit writing operation repeated until the data writing is completed for at least one of the selected memory cells.
Alternatively, the setting condition stored in the stored unit has a voltage amplitude of a pulse voltage signal that is applied to the selected word line in the unit writing operation, and a voltage application time of the pulse voltage signal varied according to the number of times of the designation of the unit writing operation repeated until the data writing is completed for at least one of the selected memory cells.
According to the non-volatile semiconductor memory device above, the characteristic of each lot can be discriminated by the number of times of the designation of the unit writing operation repeated until the completion of the first judging operation, and the setting condition can be changed correspondingly. As a result, high-precision data writing is ensured.